Search - FPGA 128

[VHDL-FPGA-Verilog] 基于FPGA的128细分的步进电机驱动程序

Description: 基于FPGA的128细分的步进电机驱动程序
Platform: | Size: 787587 | Author: F599GTB | Hits:

[Other] flash_write_tool

Description: 这是一个通过jatg线从PC机下载Fpga与cpu文件到设备的程序。下载的文件保存到串行128K的flash中。-This is a line through jatg downloaded from the PC and cpu Fpga documents to the equipment. Download the file to the serial flash 128 K were.
Platform: | Size: 3570688 | Author: 田华 | Hits:

[SCM] 12864zongxian

Description: 单片机与FPGA控制128*64液晶显示程序，用总线方式控制
Platform: | Size: 3072 | Author: zhouding | Hits:

[VHDL-FPGA-Verilog] adder.tar

Description: veriog实现的128位高速加法器，fpga实现-veriog realize high-speed 128-bit adder, fpga realize
Platform: | Size: 4096 | Author: 枫叶鹏 | Hits:

[Software Engineering] FPGA_SDR_Sdram_LED

Description: 针对主控制板上存储器(SRAM) 存储的数据量小和最高频率低的情况,提出了基于SDR Sdram(同步动态RAM) 作为主存储器的LED 显示系统的研究。在实验中,使用了现场可编程门阵列( FPGA) 来实现各模块的逻辑功能。最终实现了对L ED 显示屏的控制,并且一块主控制板最大限度的控制了256 ×128 个像素点,基于相同条件,比静态内存控制的面积大了一倍,验证了动态内存核[7 ]的实用性。-For the main control board memory (SRAM) a small amount of stored data and the highest frequency of low, based on SDR Sdram (Synchronous Dynamic RAM) as the main memory of the LED display systems. In the experiment, the use of field programmable gate array (FPGA) to realize the logic function of each module. The eventual realization of L ED display control, and a master control panel to maximize the control of the 256 × 128 pixels point, based on the same conditions than the static memory control area has doubled, to verify the dynamic memory of nuclear [7 ] the practicality.
Platform: | Size: 510976 | Author: 郑宏超 | Hits:

[VHDL-FPGA-Verilog] xd_lcd_comp

Description: 一款240＊128的LCD模块在ALTERA　FPGA　NIOS中的应用，自己写的AVALON总线IP，包括所有源码，可轻松用于NIOS中，供大家参考-A 240* 128 LCD module in the ALTERA FPGA NIOS application, write your own AVALON Bus IP, including all source code can be easily used in NIOS for reference
Platform: | Size: 13312 | Author: 张敏 | Hits:

[source in ebook] FFT

Description: 用c实现FFT算法，通过修改该程序可实现32点，64点，128点的FFT运算-With c realize FFT algorithm, by modifying the program to achieve 32 points, 64 points, 128 points FFT computation
Platform: | Size: 14336 | Author: xiuxiu | Hits:

[VHDL-FPGA-Verilog] Lcd-12864

Description: 这是一个用ALTER公司FPGA控制外部128×64液晶的程序，很实用，希望大家下载！-This is a company with FPGA control ALTER external 128 × 64 LCD procedures, it is useful, I hope you download!
Platform: | Size: 2652160 | Author: 裴跃生 | Hits:

[VHDL-FPGA-Verilog] lcd

Description: 用sopc技术实现对128*64的lcd液晶显示。这里是它的程序。 -Sopc technology used for implementation of 128* 64 LCD lcd. Here is the procedure.
Platform: | Size: 1024 | Author: zlw | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: verilog 128位突发4. sdr fpga控制器-verilog 128 bit unexpected 4. sdr fpga controller
Platform: | Size: 119808 | Author: pudnrtest | Hits:

[Other Embeded program] FPGALCD

Description: FPGA控制LCD128*64程序，时序已仿真引脚锁定，并在硬件能够上实现汉字显示。-FPGA control LCD128* 64 procedures have been timing simulation, and hardware to achieve display of Chinese characters.
Platform: | Size: 1242112 | Author: 李恺君 | Hits:

[VHDL-FPGA-Verilog] 1602_jp

Description: FPGA lcd显示程序，可以扫描键盘输入，并在lcd上显示，-FPGA lcd display program, you can scan the keyboard input and display in lcd,
Platform: | Size: 478208 | Author: zdy | Hits:

[VHDL-FPGA-Verilog] 12864

Description: 基于VHDL语言，控制液晶12864显示的源程序，非常好用。-Based on the VHDL language, control of liquid crystal display source code 12864, very easy to use.
Platform: | Size: 2476032 | Author: qiuhaimei | Hits:

[VHDL-FPGA-Verilog] lcd_driver

Description: 用FPGA控制12864液晶输出时钟信息很好可以根据自己的需要更改 -12864 LCD control with FPGA clock output information can be very good according to their need to change the
Platform: | Size: 406528 | Author: 刘军鹏 | Hits:

[VHDL-FPGA-Verilog] aes

Description: 高级加密标准AES的FPGA实现，支持128，256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
Platform: | Size: 87040 | Author: dinxj | Hits:

[VHDL-FPGA-Verilog] FFT_128_floating_point

Description: 基于Altera FPGA 的FFT128浮点运算模块(veriolg HDL+C51) (开发环境：KeilC51+Quartus7.2）-The module of 128 floating-point FFT based on Altera FPGA(veriolg HDL+C51) （Development environment：KeilC51+Quartus7.2）
Platform: | Size: 8317952 | Author: ch | Hits:

[VHDL-FPGA-Verilog] memtest

Description: 在数字系统中，一般存在多个芯片，利用不同的特点用于实现不同的功能，一般都包含CPU,FPGA,AD,DA,memory，ASSP（专用标准模块）,ASIC等。CPU用于进行智能控制，FPGA进行硬件算法处理和多设备接口，AD进行模数转换，DA进行数模转换，memory存储临时数据。因此，FPGA如何与其他芯片进行通讯是重要的设计内容。数据输入，数据输出，双向通讯，指令传递，地址管理，不同时钟的异步通讯问题等等都需要处理。最基本的MEMORY如SRAM(128KX8bbit静态存储器628128)涉及到其中的输入，输出，双向通讯，地址管理问题，具有很强的代表性。在同步数字系统中更大量用到FIFO,SDRAM等等。其中FIFO使用方便简单，用处很广。在QUARTUSII软件库中，就有各种FPGA片内MEMORY供使用。但是FPGA的片内MEMORY容量太有限，因此外部MEMORY也是经常需要的。因此，本程序让大家学习控制芯片内外的MEMORY,为与其他智能设备的通讯学习打下基础。-In the digital system, generally there are several chips, the use of different features used to implement different functions, generally includes CPU, FPGA, AD, DA, memory, ASSP (application specific standard module), ASIC and so on. CPU is used for intelligent control, FPGA hardware algorithm processing and multi-device interface, AD to ADC, DA for digital-analog conversion, memory to store temporary data. Therefore, FPGA how to communicate with other chips are important design elements. Data input, data output, two-way communication, instruction delivery, address management, different clock asynchronous communication problems, and so have to deal with. If the most basic MEMORY SRAM (128KX8bbit static memory 628 128) which involved the input, output, bi-directional communication, address management issues, with strong representation. In synchronous digital systems a lot more use FIFO, SDRAM, etc.. One simple and easy to use FIFO, use very broad. In QUARTUSII software library, there ar
Platform: | Size: 223232 | Author: 平凡 | Hits:

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